module  cordic(
  input                   clk          ,// 系统时钟
  input                   rst_n        ,// 系统异步复位，低电平有效

  input   signed  [15:0]  x            ,// x坐标值
  input   signed  [15:0]  y            ,// y坐标值

  output  signed  [15:0]  p             // 迭代后的角度
  );
wire   signed  [15:0]  angle [15:1];
reg    signed  [15:0]  x_r         ;
reg    signed  [15:0]  y_r         ;
reg    signed  [15:0]  angle_remain;
reg    signed  [1 :0]  quadrant_r  ;
// 基准角度值 pi为单位 且 放大了 100000倍
assign {
angle[1],angle[2],angle[3] ,angle[4] ,angle[5] ,angle[6] ,angle[7] ,
angle[8],angle[9],angle[10],angle[11],angle[12],angle[13],angle[14],angle[15]
} = {
16'sd25000,16'sd14758,16'sd07797,16'sd03958,16'sd01986,16'sd00994,16'sd00497,
16'sd00248,16'sd00124,16'sd00062,16'sd00031,16'sd00015,16'sd00007,16'sd00003,16'sd00001
};
// 寄存输入值
always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    x_r       <= 0;
    y_r       <= 0;
    out_valid <= 0;
  end
  else if (conditions) begin
    
  end
end

endmodule